Whitepaper: A Study of the Impact of Line Edge Roughness on Metal Line Resistance using Virtual Fabrication

BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitches, since electrons are more likely to be scattered by the metal line surface if they are closer to the surface. Metal line CD optimization and varying the metal material selection can be used to relieve this problem. However, metal line CD is not only limited by the metal pitch but also by a trade off with the line-to-line capacitance, so there is limited room for adjusting each of these parameters. Different metal materials can be used to resolve this problem, but time is required during process development to make these newer metals compatible with current semiconductor BEOL process technology. Line edge roughness is also an important factor in determining electron surface scattering and subsequent line resistivity. In this study, we investigated the impact of LER on metal line resistance by varying metal line CDs and metal line materials during process modeling split experiments.