• Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance

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  Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance

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• The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

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  The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

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• A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond

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  A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond

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• Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

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  Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

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• Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

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  Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

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• Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models

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  Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models

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• A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

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  A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

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• A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates

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  A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates

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• Influence of SiGe on Parasitic Parameters in PMOS

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  Influence of SiGe on Parasitic Parameters in PMOS

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