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• CMOS Area Scaling and the Need for High Aspect Ratio Vias

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• Process Modeling Exploration for 8 nm Half-Pitch Interconnects

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• Innovative Solutions to Increase 3D NAND Flash Memory Density

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• Effects of a Random Process Variation on the Transfer Characteristics of a Fundamental Photonic Integrated Circuit Component

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• N7 FinFET Self-Aligned Quadruple Patterning Modeling

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• Understanding the Effect of Variability in Bulk FinFET Device Performance

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• Self-Aligned Block and Fully Self-Aligned Via for iN5 Metal 2 Self-Aligned Quadruple Patterning

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• Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

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